A low jitter clock and data recovery with a single edge sensing Bang-Bang PD
نویسندگان
چکیده
منابع مشابه
Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits
Clock and data recovery (CDR) circuits incorporating bangbang (binary) phase detectors (PDs) have recently found wide usage. In contrast to their linear counterparts, bang-bang PDs relax the speed and precision required of flipflops and other circuits in the signal path, reducing the complexity and the power dissipation. However, the heavily nonlinear nature of these PDs makes the loop analysis...
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Version 1c, 4 May 2010 High speed serial data links are expected to transmit data at very high rates with very high fidelity. Today speeds approaching 10 Gb/s are becoming common with 40 Gb/s on the horizon. Typically, a maximum bit-error rate (BER) of 10–12-10–15 is required. Verifying such a small BER with direct simulation is quite impractical. Instead, a procedure is presented that separate...
متن کاملModeling of Jitter Characteristics for the Second Order Bang-Bang CDR
Bang-Bang clock and data recovery (BBCDR) circuits are hard nonlinear systems due to the nonlinearity introduced by the binary phase detector (BPD). The specification of the CDR frequency response is determined by jitter tolerance and jitter transfer. In this paper, jitter transfer and jitter tolerance of the second-order BBCDR are characterized by formulating the time domain waveforms. As a re...
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A Bang-Bang Clock-Data Recovery (CDR) for 10 Gb/s optical transmission systems is presented. A direct modulated architecture is used for the design. Its loop characteristics can be derived using an analogy to 61 theory. The circuit was produced and measured in a commercial 0.25μm BiCMOS technology with a transition frequency fT=70 GHz.
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A 10Gb/s Full On-chip Bang-Bang Clock and Data Recovery System Using an Adaptive Loop Bandwidth Strategy. (August 2009) Hyung-Joon Jeon, B.S., Seoul National University Chair of Advisory Committee: Dr. Jose Silva-Martinez As demand for higher bandwidth I/O grows, the front end design of serial link becomes significant to overcome stringent timing requirements on noisy and bandwidthlimited chann...
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ژورنال
عنوان ژورنال: IEICE Electronics Express
سال: 2014
ISSN: 1349-2543
DOI: 10.1587/elex.11.20140088